Versatile Imaging Architecture Based on a System on Chip

In this paper, a novel architecture dedicated to image processing is presented. The most original aspect of the approach is the use of a System On Chip implemented in a FPGA. We show the main advantages of such a system based on a CMOS imaging device and a programmable chip. With its structure, the system proposes a high degree of versatility and allows the implementation of parallel image processing algorithms. As a result, a Window Of Interest (WOI) module is detailed. Architecture overview In this paper, an embedded imaging architecture based on a combination of CMOS imager and FPGA is proposed. Traditionally, the image is transduced by a sensor (camera), converted and stored (image grabber) and processed on a host computer[2]. In our approach, all early-vision processing is performed in the sensor. This kind of sensor composed of a camera and an embedded processing unit, is currently called a smart sensor. The architecture presented in this paper can be considered as a development platform for a smart image sensor based on a System-On-Chip approach. Based on the active vision concept, our approach consists in integrating the control of the imager in the perception loop, especially in the early vision processes. By integration of early processing and active vision mechanisms, close to the imager, a reactive sensor can be designed. The objective is to adapt sensor attitude to change in the environment and the current task to be performed. With such a smart sensor, it is possible to perform basic processing and selection of relevant features closed to the imager. This faculty is able to reduce sensor communication flow which is a significant problem of vision sensors [1]. But vision tasks are numerous and varied, and the choice of a versatile architecture based on a reprogramable chip becomes natural. In our case, the notion of SOC (System On Chip) describes the whole system. It is well known that most vision applications are often focused on several small image areas and consequently acquisition of the whole image is not necessary. From this definition, it is evident that one of the main goals of an efficient vision sensor is to select windows of interest (WOI) in the image and concentrate processing resources on these. Indeed, the notion of local study is predominant. This notion is crucial for the choice of the imaging technology. CCD and CMOS are the two most common technologies used today in industrial digital cameras. 1 The term ”early vision” describes all processes except a high-level decision. It is different from binarization, convolution or other classical low-level processes A particularity of CMOS imagers is to adopt a digital memory style readout, using row decoders and column amplifiers. Random access of pixel values becomes possible, allowing selective readout of windows of interest. In this way and in contrast to CCD imagers, it is possible to obtain a high speed imaging capability by addressing only a small region in the image. The main advantages of CMOS imagers are broad dynamic range, random access readout, easy integration, and low blooming. Design adopted The central idea in our sensor is that visual tasks can be broken down into a sequence of simpler subtasks. Consequently the principle consists in having a collection of routines that represent different kinds of basic image processing subfunctions. These can then be composed to subserve more elaborate goal-directed programs. In our approach, the sub-functions are implemented in a FPGA so that they can be changed easily. The global processing system is composed of SOPC by which an entire system of components is put on a single chip (FPGA). The whole architecture is shown in Figure 1 and presents the different modules. The integration of the camera is done as shown in Figure 2. Fig. 1. Architecture of the sensor The design objective presented in this paper was to create a flexible interface between the imaging device board(Fig. ??) and a host computer. This design exploits the advantages of the SOC cited above in order to allow software control of the acquisition chain. The design is based on a master entity which synchronizes and defines the control parameters of a set of modules. This set of modules acts on various points of the acquisition chain. The master entity is synthesized by a NIOS c © soft core processor and its role is then easily defined by the software. Application : Enhanced Windowing This section presents the results on the WOI generation module. As explained below, this module generates the